package ChiselStudy

import chisel3._
import chisel3.util._


class testIO extends Bundle {
  val a = UInt(3.W)
  val b = UInt(3.W)
}

class VaildStudy extends Module{
  val io = IO(new Bundle{
    val en = Input(UInt(1.W))
    val a = Input(UInt(3.W))
    val b = Input(UInt(3.W))
    val test = ValidIO(new testIO())
  })

  io.test.valid := Mux(io.en === 1.U, 1.U, 0.U)

  io.test.bits.a := io.a
  io.test.bits.b := io.b

}

object VaildStudy_Gen extends App {
  println("Generating the adder hardware")
  (new chisel3.stage.ChiselStage).emitVerilog(new VaildStudy(),Array("--target-dir", "generated/VaildStudy"))
}